The present invention relates to a method for fabricating a MOS semiconductor device having three types of gate insulating films of different thicknesses.
Conventionally, a process in which two types of gate insulating films having different thicknesses are formed selectively on one chip has been used commonly for a MOS semiconductor device. In the generation of 0.18-xcexcm design rules, e.g., a MOSFET having a thin-film gate insulating film with a thickness of about 3.5 nm has been provided for an internal circuit operating at 1.8 V, while a MOSFET having a thick-film gate insulating film with a thickness of about 8 nm has been provided for an input/output circuit operating at 3.3 V (see pp.2-3 and FIGS. 1A to 1H of Japanese Laid-Open Patent Publication No. HEI 1-168054).
FIGS. 13A to 13C are cross-sectional views illustrating the individual process steps of a method for fabricating a semiconductor device according to a first conventional embodiment, specifically a method for fabricating a MOS semiconductor device having two types of gate insulating film having different thicknesses.
First, as shown in FIG. 13A, a heat treatment is performed in an oxidizing atmosphere with respect to a silicon substrate 10 having the active region of the MOSFET for the internal circuit (hereinafter referred to as the internal MOSFET active region) and the active region of the MOSFET for the input/output circuit (hereinafter referred to as the input/output MOSFET active region). As a result, a surface of the silicon substrate 10 is thermally oxidized so that a first gate insulating film 11 having a thickness of about 6 nm is formed on each of the internal MOSFET active region and the input/output MOSFET active region.
Next, as shown in FIG. 13B, wet etching using a solution containing a hydrofluoric acid is performed with respect to the first gate oxide film 11 by using a resist pattern 12 covering the input/output MOSFET active region as a mask, thereby removing the first gate oxide film 11 on the internal MOSFET active region therefrom. This exposes the substrate surface in the internal MOSFET active region.
After the resist pattern 12 is then removed, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate 10, as shown in FIG. 13C. Since the first gate oxide film 11 has been formed on the input/output MOSFET active region, the substrate surface in the internal MOSFET active region is thermally oxidized. This allows a second gate oxide film 13 having a thickness of about 3.5 nm to be formed on the internal MOSFET active region. On the other hand, the first gate oxide film 11 is increased in thickness to about 8 nm. Accordingly, the second gate oxide film 13 is thinner than the first gate oxide film 11 that has been increased in thickness.
Thereafter, a gate electrode, source/drain electrodes, an interlayer insulating film, metal wiring, and the like are formed by using well-known techniques, though they are not depicted, whereby the fabrication of the semiconductor device comprising the input/output MOSFET having the relatively thick first gate oxide film 11 and the internal MOSFET having the relatively thin second gate oxide film 13 is completed.
As the gate insulating film of the internal circuit is reduced in thickness with the miniaturization of the MOSFET, however, the power consumption of the internal circuit of the first conventional embodiment tends to increase due to an increased gate leakage current. Consequently, it has become difficult to enhance the performance of a MOS semiconductor device represented by a system LSI, while reducing both of the size (increasing the degree of integration) and power consumption thereof.
To reduce both of the size and power consumption of the internal circuit, there has been examined a method of constituting the internal circuit by two MOSFETs, one of which is a MOSFET wherein an enhanced driving ability achieved by a reduction in the thickness of the gate insulating film is a higher priority and the other of which is a MOSFET wherein reduced power consumption is a higher priority, and selectively using the two MOSFETs depending on an object or a use. In suppressing an increase in power consumption resulting from a gate leakage current, it is most effective to increase the thickness of the gate insulating film. It becomes therefore necessary to individually form two types of gate insulating films having different thicknesses. In the generation of 0.10-xcexcm design rules, e.g., size reduction and lower power consumption can be achieved by using a thin-film gate insulating film with a thickness of 1.6 nm and a thick-film gate insulating film with a thickness of 2.4 nm as the gate insulating films of a MOSFET composing an internal circuit operating at 1.0 to 1.2 V. On the other hand, an input/output circuit required to operate at a high voltage of 3.3 V, 2.5 V, or the like needs a MOSFET having a gate insulating film with a thickness of about 8 nm. Thus, it has become necessary to individually form the total of three gate insulating films having different thicknesses for the internal circuit and the input/output circuit in one chip.
To implement the three types of gate insulating films formed individually, there has been proposed a method for fabricating a semiconductor device using three thermal oxidation steps (see pp. 79-80 (especially FIG. 2) of A. Ono et al., A Multi-gate Dielectric Technology Using Hydrogen Pre-treatment for 100 nm generation System-on-a-Chip, 2001 Symposium on VLSI Technology Digest of Technical Papers).
FIGS. 14A to 14C and FIGS. 15A to 15C are cross-sectional views illustrating the individual process steps of a method for fabricating a semiconductor device according to a second conventional embodiment, specifically a method for fabricating a MOS semiconductor device having three types of gate insulating films of different thicknesses.
First, as shown in FIG. 14A, an isolating region (not shown) is formed in silicon substrate 20 by LOCOS or the like so as to partition the silicon substrate 20 into an input/output MOSFET active region, a first internal MOSFET active region, and a second internal MOSFET active region. Then a mask nitride film and a pad oxide film (each of which is not shown) used for the formation of the isolation region are removed by wet etching, whereby a substrate surface in each of the MOSFET active regions is exposed.
Next, as shown in FIG. 14B, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate 20 having the input/output MOSFET active region, the first internal MOSFET active region to be provided with a thick-film gate insulating film, and the second internal MOSFET active region to be provided with a thin-film gate insulating film. This thermally oxidizes a surface of the silicon substrate 20 and thereby allows a first gate oxide film 21 to be formed individually on each of the input/output MOSFET active region, the first internal MOSFET active region, and the second internal OSFET active region.
Next, as shown in FIG. 14C, wet etching using a solution containing a hydrofluoric acid is performed with respect to the first gate oxide film 21 by using, as a mask, a first resist pattern 22 covering the input/output MOSFET active region, thereby removing the first gate oxide film 21 on each of the first and second internal MOSFET active regions therefrom and exposing the substrate surface in each of the first and second internal MOSFET active regions.
After the first resist pattern 22 is then removed, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate 20, as shown in FIG. 15A. Since the first gate oxide film 21 has been formed on the input/output MOSFET active region, the substrate surface in each of the first and second internal MOSFET active regions is thermally oxidized. This allows a second gate oxide film 23 to be formed individually on each of the first and second internal MOSFET active regions. At the same time, the first gate oxide film 21 is slightly increased in thickness. Accordingly, the second oxide film 23 is thinner than the first gate oxide film 21 that has been increased in thickness.
Next, as shown in FIG. 15B, wet etching using a solution containing a hydrofluoric acid is performed with respect to the second gate oxide film 23 by using, as a mask, a second resist pattern 24 covering the input/output MOSFET active region and the first internal MOSFET active region, thereby removing the second gate oxide film 23 on the second internal MOSFET active region.
After the second resist pattern 24 is then removed, a heat treatment is performed in an oxidizing atmosphere with respect to the silicon substrate 20, as shown in FIG. 15C. Since the first gate oxide film 21 has been formed on the input/output MOSFET active region and the second gate oxide film 23 has been formed on the first internal MOSFET active region is thermally oxidized. This allows a third gate oxide film 25 to be formed on the second internal MOSFET active region. At the same time, each of the first and second gate oxide films 21 and 23 is slightly increased in thickness. Accordingly, the third gate oxide film 25 is thinner than the second gate oxide film 23 that has been increased in thickness.
Thereafter, a gate electrode, source/drain electrodes, an interlayer insulating film, metal wiring, and the like are formed by using well-known techniques, though they are not depicted, whereby the fabrication of the semiconductor device comprising an input/output MOSFET having the relatively thickest first gate oxide film 21, a first internal MOSFET having the relatively second thickest second gate oxide film 23, and a second internal MOSFET having the relatively thinnest third gate oxide film 25 is completed.
However, the second conventional embodiment has the problems of anomalies in the characteristics of a transistor and the degradation of the reliability of a gate insulating film. A description will be given herein below to the cause for the problems with reference to the drawings. FIG. 16 shows a cross-sectional structure (in the gate width direction) of the second internal MOSFET having the thin-film gate insulating film in the semiconductor device fabricated according to the second conventional embodiment. As shown in FIG. 16, a gate electrode 27 is formed on the second internal MOSFET active region (silicon substrate 20) surrounded by an isolation region 26 with the third gate oxide film 25 (see FIG. 15C) interposed therebetween. In addition, insulating sidewalls 28 are formed on the side surfaces of the third gate oxide film 25.
In the second conventional embodiment, the substrate surface in the first internal MOSFET active region on which the thick-film gate insulating film is to be provided is exposed twice by wet etching. On the other hand, the substrate surface in the second internal MOSFET active region on which the thin-film gate insulating film is to be provided is exposed three times by wet etching. Accordingly, the roughness of the substrate surface is more conspicuous in the second internal MOSFET active region than in the first internal MOSFET active region. Moreover, the portion of the isolation region 26 which is adjacent the second internal MOSFET active region, i.e., the end portion of the isolation region 26 is more likely to be etched to a greater depth than the first internal MOSFET active region, as shown in FIG. 16. In the second internal MOSFET having the relatively thinnest third gate oxide film 25, therefore, due to an increased depth to which the end portion of the isolation region 26 is etched, the thickness of the third gate oxide film 25 becomes uneven and an electric field is localized to the portion of the third gate oxide film 25 which is adjacent the isolation region 26 during the application of a gate voltage. Such increased roughness of a substrate surface, an uneven thickness of a gate insulating film, or a localized electric field is the cause of the anomalies in the characteristics of a transistor or the degradation of the reliability of the gate insulating film. Further, the number of times of wet etching which differs from the first internal MOSFET to the second internal MOSFET, to each of which the gate voltage of the same magnitude is applied, also causes the problem that the setting of a process margin for each of the internal MOSFETs becomes difficult.
In view of the foregoing, it is therefore an object of the present invention to prevent anomalies in the characteristics of a transistor or the degradation of the reliability of a gate insulating film and allow easy setting of a process margin in the fabrication of a MOS semiconductor having three types of gate insulating films.
To attain the object, a first method for fabricating a semiconductor device according to the present invention comprises the steps of: forming a semiconductor substrate with a first active region, a second active region, and a third active region isolated from each other by an isolation region and then forming a first gate insulating film on each of the first, second, and third active regions; removing the first gate insulating film on the second active region therefrom and then forming a second gate insulating film thinner than the first gate insulating film on the second active region; after the step of forming the second gate insulating film, removing the first gate insulating film on the third active region therefrom and then forming a third gate insulating film thinner than the second gate insulating film on the third active region; and forming a first gate electrode, a second gate electrode, and a third gate electrode on the first, second, and third active regions with the first, second, and third gate insulating films interposed therebetween, respectively.
In contrast to the second conventional embodiment, the first method for fabricating a semiconductor device achieves the following effects.
Specifically, the number of times that the third active region is exposed by wet etching or the like performed to remove the gate insulating films can be reduced. This reduces the roughness of the substrate surface in the third active region. This also reduces the depth to which the region of the exposed portion of the trench isolation region which is adjacent the third active region, i.e., the end portion of the trench isolation region is etched so that the thickness of the third gate insulating film becomes uniform and the localization of an electric field to the portion of the third gate insulating film which is adjacent the trench isolation region during the application of a gate voltage is prevented. As a result, anomalies in the characteristics of a transistor or the degradation of the reliability of a gate insulating film resulting from increased roughness of a substrate surface, an uneven thickness of the gate insulating film, or the localization of an electric field can be prevented. Since the number of times that the third active region is exposed becomes equal to the number of times that the second active region is exposed, the setting of a process margin for each of the MOSFETs can be performed easily if a gate voltage of the same magnitude is applied to each of the respective MOSFETs formed in the second and third active regions.
In the first method for fabricating a semiconductor device, the isolation region may be a trench isolation region.
In the first method for fabricating a semiconductor device, the step of forming each of the first, second, and third gate insulating films preferably includes the step of thermally oxidizing a surface of each of the first, second, and third active regions.
This allows easy and reliable formation of each of the gate insulating films.
In the first method for fabricating a semiconductor device, the step of removing the first gate insulating film on the specified active region therefrom preferably includes the step of performing wet etching with respect to the first gate insulating film by using a resist pattern covering the active regions other than the specified active region as a mask.
This ensures the removal of the first gate insulating film on the specified active region therefrom, while protecting a surface (if a gate oxide film is formed thereon, the surface of the gate oxide film) of each of the other active regions.
A second method for fabricating a semiconductor device according to the present invention comprises the steps of: forming a semiconductor substrate with a first active region, a second active region, and a third active region separated from each other by an isolation region and each having a surface covered with a pad oxide film; removing the pad oxide film on the first active region therefrom and then forming a first gate insulating film on the first active region; after the step of forming the first gate insulating film, removing the pad oxide film on the second active region therefrom and then forming a second gate insulating film thinner than the first gate insulating film on the second active region; after the step of forming the second gate insulating film, removing the pad oxide film on the third active region therefrom and forming a third gate insulating film thinner than the second gate insulating film on the third active region; and forming a first gate electrode, a second gate electrode, and a third gate electrode on the first, second, and third active regions with the first, second, and third gate insulating films interposed therebetween, respectively.
In contrast to the second conventional embodiment, the second method for fabricating a second semiconductor device achieves the following effects.
Specifically, the number of times that each of the second and third active regions is exposed by wet etching or the like performed to remove the pad oxide film or the gate insulating film can be reduced. This reduces the roughness of the substrate surface in each of the second and third active regions. This also reduces the depth to which the region of the exposed portion of the trench isolation region which is adjacent each of the second and third active regions is etched so that the thickness of each of the second and third gate insulating film becomes uniform and the localization of an electric field to the portion of each of the second and third gate insulating films which is adjacent the trench isolation region is prevented during the application of a gate voltage. As a result, anomalies in the characteristics of a transistor or the degradation of the reliability of a gate insulating film resulting from increased roughness of a substrate surface, an uneven thickness of the gate insulating film, or the localization of an electric field can be prevented. Since the number of times that the third active region is exposed becomes equal to the number of times that the second active region is exposed, the setting of a process margin for each of the MOSFETs can be performed easily if a gate voltage of the same magnitude is applied to each of the respective MOSFETs formed in the second and third active regions.
In the second method for fabricating a semiconductor device, the isolation region may be a trench isolation region.
In the second method for fabricating a semiconductor device, each of the first and second active regions may be an active region of a MOSFET of an input/output circuit and the third active region may be an active region of a MOSFET of an internal circuit.
In the second method for fabricating a semiconductor device, the first, second, or third gate insulating film is preferably formed by thermally oxidizing a surface of the active region on which the gate insulating film is to be provided.
This allows easy and reliable formation of each of the gate insulating films.
In the second method for fabricating a semiconductor device, the step of removing the pad oxide on the specified active region therefrom preferably includes the step of performing wet etching with respect to the pad oxide film by using a resist pattern covering the active regions other than the specified active region as a mask.
This ensures the removal of the pad oxide film on the specified active region therefrom, while protecting a surface (if a gate oxide film is formed thereon, the surface of the gate oxide film) of each of the other active regions.